The present invention relates to highly doped polycrystalline silicon (polysilicon) technology and to a process for forming fine polysilicon patterns with a high degree of precision. In particular, the invention relates to a method of treating polysilicon material using ion implantation and rapid thermal heating or annealing techniques to provide a highly doped, low sheet resistance polysilicon structure which has a high etch rate, excellent pattern transfer and anisotropic etch characteristics.
Polycrystalline silicon has long been the most widely used gate material in MOS LSI technology. The greatest impetus to the use of polysilicon resulted from the development of the self-aligned gate technology. The self-aligned gate process involves forming the source and drain in the presence of the gate, which functions as a self-aligning dopant mask. As IC (integrated circuit) structures have been scaled to smaller and more shallow sizes, the prevalent doping process has evolved from furnace predeposition and diffusion to ion implantation. Furthermore, the need for a high melting point material which can withstand the self-aligned process temperatures has resulted in aluminum being replaced by polysilicon as the prevalent gate material. Polysilicon is widely used in both bipolar and MOS IC technology, for example in conductors, such as single-level and multi-level interconnects; in resistors; in buried contacts; and in the formation of emitter structures such as shallow, self-aligned emitters and self-aligned emitter-contact structures.
With the trend toward ever greater device densities and smaller minimum feature sizes and smaller separations in VLSI integrated circuits, the sheet resistance of multi-level interconnects and gate electrodes and other conductors becomes a primary factor affecting frequency characteristics and power consumption, and in limiting device speed. Thus, to successfully implement greater density without adversely affecting such characteristics, it is necessary to reduce the sheet resistance of the gate and conductor material.
Another requirement which must be met to achieve the increasingly small minimum feature sizes and minimum separations is that the lithographic pattern-transfer process must be very precise. The minimum feature size and the minimum feature separation depend upon the minimum mask dimensions that are available for the particular lithographic process. This in turn depends upon various factors including the lithographic process itself and the wafer topography. Minimum feature size and separation also depend upbn the feature change associated with the particular process step.
This feature change in turn depends upon the pattern-transfer process. Anisotropic etching produces minimum size changes. In contrast, where isotropic etching is used, the final IC feature may not be at all close in size to the lithographic feature size.
Present and future polysilicon resistance requirements can be met using polysilicon sheet resistance values .ltorsim.17 ohms per square.
Unfortunately, and as is well known, the very high polysilicon doping levels which are necessary to meet such low resistance requirements have been obtained at the cost of isotropic etch behavior and imprecise pattern-transfer. For example, as reported in Davies et al, U.S. Pat. No. 4,420,344, when polysilicon is doped to a sufficiently high level so that sheet resistance is much below about 50 ohms per square (500 nm; 2.5.times.10.sup.-3 ohm-m), etching occurs preferentially along grain boundaries, etching characteristics degenerate dramatically and fine line patterning becomes impossible.
Several very undesirable results of isotropic etch behavior can be illustrated using the self-aligned silicon gate technology as an example. In the self-aligned fabrication process, the gate length establishes the channel length. If the etch process is isotropic to the polysilicon gate material and the mask outline is not transferred precisely the gate, the gate walls will be sloped or undercut. During the subsequent source/drain implantation, the tapered gate profile will be transferred to the source/drain doping profile. This sloped profile may increase the required size of the gate mask feature and require greater separation between the source and drain to prevent shorting, and may cause a variable channel length. Any one or all of these results are highly undesirable, particularly under the increasingly stringent physical and operational tolerances of scaled VLSI devices.
At least several new materials and processes have been developed in attempts to avoid the choice which classical polysilicon technology requires between low resistance and effective pattern transfer. For example, molybedenum and tungsten have been investigated as possible gate materials. See, for example, Kashiwagi, Trends in Gate Electrode Materials and Process for VLSI's of the Next Generation, J. S. T. News, Vol. 2, No. 6, pp. 30-33, December 1983.
In addition, within the last several years polycide has been substituted for polysilicon in a number of applications. Polycide is a layer of metal silicide (such as molybdenum-silicide or tungsten-silicide) over a layer of polysilicon. Presently, polycide technology can provide conductor sheet resistances of about four to seven ohms per square. Polycide, however, has several serious processing shortcomings. First, there is no known single step anisotropic etch process for polycides. The available etchants provide insufficient anisotropy for one or both of the constituent layers. Also, polysilicon etches faster than silicide and causes undercutting of the silicide, with a resulting loss in adhesion of the silicide and step coverage problems. Another consideration is the difficulty in obtaining sufficient etching selectivity with respect to an underlying oxide such as the gate oxide in the self-aligned gate process. As a result of these problems, the IC industry has been forced to develop multi-step etch processes for polycides.
Secondly, the unsatisfactory etch characteristics of annealed silicides requires that polycide etching be done prior to annealing. This requires that the anneal be performed relatively late in the fabrication process, when it may degrade existing structures, for example, by diffusing source/drain regions or other impurity regions.
The inherent shortcoming of substitutional technology such as metal silicides and the need to further develop such technologies make it highly desirable to extend the classic polysilicon technology by providing anisotropic etch characteristics at low resistance, high doping levels.
Etching of relatively highly doped polysilicon can be made anisotropic, for example, by adding recombinant CCl.sub.4 to RIE or C.sub.2 F6 to plasma etching. Koike et al in Abstract No. 213 for the Electrochemical Society Spring Meeting, Montreal, Canada, May 9-14, 1982, reported anisotropic plasma etching of doped polysilicon using various carbon-containing etching gases such as C.sub.2 ClF.sub.5. However, the reported etch data is for samples having sheet resistances which are greater than approximately 25 ohms per square and, typically, greater than approximately 50 ohms per square. Thus, the paper does not consider the very highly doped sheet resistances (approximately 20 ohms per square or lower; doping impurity concentrations .gtoreq.10.sup.20 cm.sup.-3) which are of primary interest in terms of extending classical polysilicon technology. Furthermore, it is highly undesirable to use carbon in the plasma-producing gas, for it tends to form polymerized deposits on the poly and is very difficult to remove from vertical walls. Oxygen can be added to the etching gas mixture to clear the carbon, but oxygen increases the lateral etching tendency which carbon is intended to eliminate.
Recently, Schwartz and Schaible reported an investigation of etching rates and profiles for highly doped silicon. See The Effects of Arsenic Doping and Reactive Ion Etching of Silicon in Chlorinated Plasmas, published in the Journal of the Electrochemical Society, Vol. 130, No. 9, September 1983, pp. 1898-1905. In n-type polysilicon (concentrations .gtoreq.10.sup.20 cm.sup.-3), undercutting was observed to be an inherent problem. The maximum undercut was approximately one-half as great using CCl.sub.4 etching gas as for Cl.sub.2 etching gas. However, any advantage in the lessened undercutting is probably offset by the use of carbon. Furthermore, even for CCl.sub.4 etching gas, undercutting ranged from approximately 0.25 to 0.5 for impurity concentrations .gtoreq.10.sup.20 cm.sup.-3, which is highly undesirable.
Schwartz et al did not determine what mechanism is responsible for the undercutting (isotropy) associated with very heavily doped silicon. They did conclude that the impurity doping somehow increased the chemical component of the etching reaction and the dependence of etch rate on temperature. This article is believed to be representative of the current state of the polysilicon technology in that it evidences a lack of awareness of the precise operative mechanism which is responsible for the undesired isotropic etch characteristics of highly doped silicon. Nor is there any recognition or suggestion that rapid thermal annealing can provide a solution to the resistance/pattern transfer dilemma.
In view of the above, it is an object of the present invention to extend the polysilicon technology by providing a process for treating polysilicon which provides very highly doped polysilicon which is nonetheless characterized by anisotropic etching.
It is another object of the present invention to provide a process for treating polysilicon which provides an optimized combination of low resistance, high etch rate, and anisotropic etch characteristics.
It is yet another object of the present invention to provide a process for providing optimum anisotropy and/or etch rate and/or sheet resistance by rapid thermal annealing of implanted polysilicon.
It is still another object of the present invention to provide a method for determining the precise combination of parameters which are necessary to provide optimum anisotropy and/or etch rate and/or sheet resistance for a given doping level and annealing temperature.